Chip tester, method for providing timing information, test fixture set, apparatus for post-processing propagation delay information, method for post-processing delay information, chip test set up and method for testing devices under test

ABSTRACT

A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.

BACKGROUND OF THE INVENTION

The present invention is generally related to a chip tester, a methodfor providing timing information, a test fixture set, an apparatus forpost-processing propagation delay information, a method forpost-processing delay information, a chip test set up and a method fortesting devices under test.

In an embodiment, the present invention is related to a fixture delaycalibration in a driver sharing test environment.

In the field of testing devices it is sometimes advantageous to connecta plurality of devices under test to a common line. Consequently,terminals of at least two devices under test are connected to a commonchannel of a chip tester. These terminals are typically designated asshared terminals. However, some of the terminals of the devices undertest are connected to channels of the chip tester via individual(non-shared or unshared) lines. Thus, in typical setups there are bothshared terminals of devices under test, which are connected to the chiptester via a shared line and unshared terminals, which are connected tochannels of the chip tester via unshared lines.

However, the sharing of lines for connecting a plurality of devicesunder test to a single channel brings along significant difficulties inobtaining reliable test results.

SUMMARY

According to an embodiment, a chip tester for testing at least twodevices under test connected to the chip tester, wherein at least afirst terminal of the a first device under test and a first terminal ofa second device under test are connected to a first channel of the chiptester via a shared line, wherein a second terminal of the first deviceunder test is connected to a second channel of the chip tester via anunshared line, and wherein a second terminal of the second device undertest is connected to a third channel of the chip tester via an unsharedline, may have a timing calculator for generating a timing informationfor the channels of the chip tester, wherein the timing calculator isadapted to acquire a propagation delay difference information describinga difference between, on the one hand, a propagation delay from a firstchannel port of the chip tester to the first terminal of the firstdevice under test and, on the other hand, a propagation delay from thefirst channel port of the chip tester to the first terminal of thesecond device under test, and wherein the timing calculator is adaptedto provide timing information to adjust a timing shift between timingsof the second channel and the third channel on the basis of thepropagation time difference information; and a channel moduleconfigurator adapted to configure the second channel and/or the thirdchannel of the chip tester on the basis of the timing information.

According to another embodiment, a test fixture set may have a deviceunder test board for providing an electrical connection between a chiptester and at least two devices under test, wherein device under testboard may have a first device under test contact element for providing adetachable electrical contact between the device under test board and afirst device under test, a second device under test contact element forproviding a detachable electrical contact between the device under testboard and a second device under test, a third device under test contactelement for providing a detachable electrical contact between the deviceunder test board and the first device under test, a fourth device undertest contact element for providing a detachable electrical contactbetween the device under test board and the second device under test, afirst chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, asecond chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, and athird chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, whereinthe first device under test contact element and the second device undertest contact element are both electrically connected to the first chiptester contact element via a shared line; wherein the third device undertest contact element is electrically connected to the second chip testercontact element; wherein the fourth device under test contact element iselectrically connected to the third chip tester contact element; and adata exchange medium or data stream for usage with the chip tester, thedata exchange medium or data stream comprising an effective propagationdelay information describing an effective propagation delay between thethird device under test contact element and the second chip testercontact element and an effective propagation delay between the fourthdevice under test contact element and the third chip tester contactelement, wherein the effective propagation delays are based on actualpropagation delays and wherein at least one of the effective propagationdelays is changed with respect to a corresponding actual propagationdelay, such that the deviation of the effective propagation delay fromthe actual propagation delay reflects a difference between, on the onehand, a propagation delay between the first chip tester contact elementand the first device under test contact element and, on the other hand,a propagation delay between the first chip tester contact element andthe second device under test contact element.

According to another embodiment, an apparatus for post-processing aplurality of propagation delay values of a device under test board for achip tester, wherein the device under test board is adapted to providean electrical connection between a chip tester and at least two devicesunder test, and wherein the device under test board has a first deviceunder test contact element for providing a detachable electrical contactbetween the device under test board and a first device under test, asecond device under test contact element for providing a detachableelectrical contact between the device under test board and a seconddevice under test, a third device under test contact element forproviding a detachable electrical contact between the device under testboard and the first device under test, a fourth device under testcontact element for providing a detachable electrical contact betweenthe device under test board and the second device under test, a firstchip tester contact element for providing a detachable contact betweenthe device under test board and the chip tester, a second chip testercontact element for providing a detachable contact between the deviceunder test board and the chip tester, a third chip tester contactelement for providing a detachable electrical contact between the deviceunder test board and a chip tester, wherein the first device under testcontact element and the second device under test contact element areboth electrically connected to the first chip tester contact element viaa shared line, wherein the apparatus may have a propagation delaydeterminator for acquiring an original propagation delay valuedescribing a propagation delay between the fourth device under testcontact element and the third chip tester contact element; a propagationdelay difference value determinator for acquiring a propagation delaydifference value describing a difference between, on the one hand, apropagation delay between the first chip tester contact element and thefirst device under test contact element and, on the other hand, apropagation delay between the first chip tester contact element and thesecond device under test contact element; and a propagation delaymodifier for modifying the original propagation delay value on the basisof the propagation delay difference value.

According to another embodiment, a method for providing timinginformation for adjusting a timing of a chip tester operating in aconfiguration in which at least a first terminal of a first device undertest and a first terminal of a second device under test are connected toa first channel of the chip tester via a shared line and in which asecond terminal of the first device under test is connected to a secondchannel of the chip tester via an unshared line and in which a secondterminal of the second device under test is connected to a third channelof the chip tester via an unshared line, may have the steps of acquiringa propagation delay difference information describing a propagation timedifference between, on the one hand, the propagation delay from a firstchannel port of the chip tester to the first terminal of the firstdevice under test, and, on the other hand, a propagation delay from thefirst channel port of the chip tester to the first terminal of thesecond device under test; and providing the timing information to adjusta timing shift between timings of the second channel and the thirdchannel on the basis of the propagation time difference information.

According to another embodiment, a method for post-processing aplurality of propagation delay values for a device under test board fora chip tester, wherein the device under test board is adapted to providean electrical connection between the chip tester and at least twodevices under test, and wherein the device under test board has a firstdevice under test contact element for providing a detachable electricalcontact between the device under test board and a first device undertest, a second device under test contact element for providing adetachable electrical contact between the device under test board and asecond device under test, a third device under test contact element forproviding a detachable electrical contact between the device under testboard and the first device under test, a fourth device under testcontact element for providing a detachable electrical contact betweenthe device under test board and the second device under test, a firstchip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, asecond chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, and athird chip tester contact element for providing a detachable electricalcontact between the device under test board and a chip tester, whereinthe first device under test contact element and the second device undertest contact element are both electrically connected to the first chiptester contact element via a shared line, may have the steps ofacquiring an original propagation delay value describing a propagationdelay between the fourth device under test contact element and the thirdchip tester contact element; acquiring a propagation delay differencevalue describing a difference between, on the one hand, a propagationdelay between the first chip tester contact element and the first deviceunder test contact element, and, on the other hand, a propagation delaybetween the first chip tester contact element and the second chip testercontact element; and modifying the original propagation delay valueusing the propagation delay difference value.

An embodiment of the present invention creates a chip tester for testingat least two devices under test. The chip tester comprises a firstchannel and a second channel, a timing calculator for generating atiming information for the channels of the chip tester and a channelmodule configurator. The timing calculator is adapted to generate atiming information for the channels of the chip tester, and is furtheradapted to obtain a propagation delay difference information describinga difference between, on the one hand, a propagation delay from a firstchannel port of the chip tester to a first terminal of the first deviceunder test (DUT) and, on the other hand, a propagation delay from thefirst channel port of the chip tester to a first terminal of a seconddevice under test. The timing calculator is adapted to provide a timinginformation for a second channel of the chip tester connected to thefirst device under test or to the second device under test on the basisof the propagation delay difference information. The channel moduleconfigurator is adapted to configure the second channel of the chiptester on the basis of the timing information.

Moreover, the present invention creates means and methods according tothe parallel independent claims. Besides, embodiments of the presentinvention are defined by the dependent claims.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will subsequently be describedtaking reference to enclosed figures, in which

FIG. 1 shows a schematic diagram of a chip tester, according to anembodiment of the present invention;

FIGS. 2 a to 2 c show possible configurations of two devices under test,according to embodiments of the present invention;

FIG. 3 shows a block schematic diagram of a chip tester, connected totwo devices under test, according to an embodiment of the presentinvention;

FIG. 4 a shows a graphical representation of an exemplary wave form,which may be present at a channel port of a chip tester according to anembodiment of the present invention;

FIG. 4 b shows a graphical representation of an exemplary wave form,which may be present at a channel port of a chip tester according to anembodiment of the present invention;

FIG. 4 c shows a graphical representation of an exemplary wave form,which may be present at a channel port of a chip tester according to anembodiment of the present invention;

FIG. 4 d shows a graphical representation of exemplary wave forms, whichmay be present at the channel ports of a chip tester according to anembodiment of the present invention;

FIG. 4 e shows a graphical representation of exemplary wave forms, whichmay be present at terminals of the first device under test according toan embodiment of the present invention;

FIG. 4 f shows a graphical representation of exemplary wave forms, whichmay be present at terminals of the second device under test according toan embodiment of the present invention;

FIG. 5 shows a graphical representation of an output wave form and asample reference time, which may be present in a chip tester accordingto an embodiment of the present invention;

FIG. 6 shows a block schematic diagram of an apparatus for postprocessing propagation delay values, according to an embodiment of thepresent invention;

FIG. 7 a shows a graphical representation of an actual dut board andpossible corresponding original propagation delay value files, accordingto an embodiment of the present invention;

FIG. 7 b shows a graphical representation of a possible effective dutboard and a possible corresponding effective propagation delay valuefile, according to an embodiment of the present invention;

FIG. 7 c shows a graphical representation of another possible effectivedevice under test board and possible corresponding effective propagationdelay value files, according to an embodiment of the present invention;

FIG. 7 d shows an example of an extended configuration for testing twoduts;

FIG. 8 shows a graphical representation of an averaging scheme fordetermining an average propagation delay difference value, according toan embodiment of the present invention;

FIG. 9 shows a graphical representation of a dut board set, according toan embodiment of the present invention;

FIG. 10 shows a graphical representation of a dut board comprising morethan 2 devices under test, according to an embodiment of the presentinvention;

FIG. 11 shows a flow chart of an inventive method for characterizing adut board; and

FIG. 12 shows a flow chart of a method for providing timing informationfor adjusting a timing of a chip tester, according to an embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a block schematic diagram of a chip tester according to anembodiment of the present invention. The chip tester of FIG. 1 isdesignated in its entirety with 100. The chip tester 100 comprises atiming calculator 110, which is adapted to obtain (e.g. to read or tomeasure) a propagation delay difference information 112. The timingcalculator 110 is further adapted to provide a timing information 114 toa channel module configurator 120. The chip tester 100 further comprisesa first channel 130 and a second channel 132, wherein a dut terminal ofthe first channel 130 is routed to a first channel port 134, and whereina dut terminal of the second channel 132 is routed to a second channelport 136. Moreover, the second channel 132 is cabled to the channelmodule configurator 120 to receive timing configuration information 140from the channel module configurator 120. Optionally the first channel130 may also be connected to the channel module configurator 120.

It should further be noted that the graphical representation of FIG. 1shows a first device under test 150 and a second device under test 160,which are connected to the chip tester 100. However, it should be notedthat the devices under test 150, 160 are naturally not part of the chiptester. However, a first terminal 152 of the first device under test 150is connected to the first terminal port 134 of the chip tester 100, andthe first terminal 162 of the second device under test 160 is alsoconnected to the first channel port 134 of the chip tester 100.Moreover, a second terminal 164 of the second device under test 160(which may be an input terminal or an output terminal, or aninput/output terminal) is cabled to the second channel port 136 of thechip tester 100. However, alternatively a second terminal 154 of thefirst device under test 150 (which may be an input terminal or an outputterminal, or an input/output terminal) is connected to the secondchannel port 136.

Based on the above structural description, the functionality of the chiptester 100 will subsequently described. The propagation delay differenceinformation 112 describes the difference between, on the one hand, apropagation delay from the first channel port 134 of the chip tester tothe first terminal 152 of the first device under test 150, and, on theother hand, a propagation delay from the first channel port 134 of thechip tester to a first terminal 162 of the second device under test.Thus, the timing calculator of the chip tester handles information abouta difference of propagation delays of a signal output at the firstchannel port 134 traveling to the first device under test 150 and to thesecond device under test 160. This information is relevant as thepropagation times between the first channel port 134 and the terminals152, 162 of the devices under test 150, 160 may be different, forexample, if the devices under test 150, 160 are connected to the firstchannel port 134 in a bus-like structure (e.g. using a commontransmission line having taps with different distances from the firstchannel port for providing the signals to the terminals 152, 162 of thedevices under test 150, 160). The timing calculator 110 is adapted toprovide a timing information for the second channel 132 of a chip testeron the basis of the propagation delay difference information 112. Thechannel module configurator is adapted to configure the second channel132 of the chip tester 110 on the basis of the timing information 114.Consequently, a timing of the second channel 132 can be adapted independence on the propagation delay difference information 112. Thus, anappropriate timing of the signals reaching the devices under test can beachieved, in spite of the different propagation delay times between thefirst channel port and the terminals 152, 162 of the first device undertest 150 and the second device under test 160.

It should be noted here that the second channel 132 can either be aninput channel, an output channel (also designated as driver channel) oran input/output channel. Moreover, it should be noted that the secondchannel 132 can be an input/output channel configured to act either asan input channel only or as an output channel only.

In the following, different configurations of the devices under testwill be described, which can be used in specific embodiments of thepresent invention.

FIG. 2 a shows a block schematic diagram of a first dut configuration. Afirst dut 150 a comprises a first input terminal 152 a and a secondinput terminal 154 a. A second device under test 160 a comprises a firstinput terminal 162 a and a second input terminal 164 a. It should benoted here that the first input terminal 152 a of the first dut 150 aand the first input terminal 162 a of the second dut 160 a are bothconnected to an output channel (driver channel) 130 a of a chip tester.Moreover, the second input port 154 a of the first dut 150 a is cabled(or electrically connected) to a second output port 132 a of a chiptester. The second input port 164 a of the second dut 160 a is furtherconnected to a third output port 138 a of the chip tester. Moreover, apropagation delay between the output channel (driver channel) 130 a (ora corresponding channel port) and the input terminal 152 a of the firstdut 150 is designated with Δtp1. A propagation delay between the outputchannel (driver channel) 130 a (or a corresponding channel port) and thefirst input terminal 162 a of the second dut 160 a is designated withΔtp2.

Naturally, the duts 150 a, 160 a may also comprise outputs, which arenot shown here for the sake of simplicity. Signals, which may be presentat the dut outputs may, for example, be input into the chip tester, andmay further be used in order to decide whether a dut fulfills a desiredspecification.

It should be noted here that the first output channel (driver channel)130 a, may, in an embodiment, be identical to the first channel 130.Moreover, the second output channel (driver channel) 132 a may beidentical to the second channel 132.

FIG. 2 b shows a block schematic diagram of another dut configuration. Afirst dut 150 b comprises an input terminal 152 b and an output terminal154 b. A second dut 160 b comprises an input terminal 162 b and anoutput terminal 164 b. The input terminals 152 b, 162 b of the first andsecond dut 150 b, 160 b are both connected to a an output channel 130 bof a chip tester. Propagation delays between the output channel 130 band the input terminals 152 b, 162 b are again designated with Δtp1 andΔtp2.

Moreover, the output terminal 154 b of the first dut 150 b is coupled(or electrically connected) with a first input channel 132 b (or aninput/output channel configured as an input) of the chip tester.Similarly, the output terminal 164 b of the second dut 160 is coupled toan input channel (or input/output channel configured as an input) 138 bof the chip tester.

It should be noted that the output channel 130 b may be identical to thefirst channel 130 and that the input channel 132 b may be identical tothe second channel 132.

FIG. 2 c shows a graphical representation of another dut configuration,which may, for example, be used for testing high speed duts. FIG. 2 cshows a configuration in which some of the input pins of the duts areshared and in which each dut further comprises at least one unsharedinput and at least one unshared output. A first dut 150 c comprises afirst shared input 152 c, a second shared input 153 c, a first unsharedinput 154 c, a second unshared input 155 c, a first output 156 c and asecond output 157 c. Similarly, a second dut 160 c comprises acorresponding first shared input 162 c, a second shared input 163 c, afirst unshared input 164 c, a second unshared input 165 c, a firstoutput 166 c, and a second output 167 c. The first shared input 152 c ofthe first dut 150 c and the first shared input 162 c of the second dut160 c are both connected, using a first shared bus line 170 c, with afirst output channel 134 c of the chip tester. Similarly, the secondshared input 153 c of the first dut 150 c and the second shared input163 c of the second dut 160 c are both connected with an output channel135 c of the chip tester using a second shared bus line 171 c. Moreover,the first output 156 c of the first dut 150 c is connected with a firstinput channel 172 c of the chip tester, the second output 157 c of thefirst dut 150 c is connected with a second input channel 173 c of thechip tester, the first output 166 c of the second dut 160 c is connectedwith a third input channel 174 c of the chip tester and the secondoutput 167 c of the second dut 160 c is connected with a fourth inputchannel 175 c of the chip tester. The first unshared input 154 c of thefirst dut 150 c is connected with a third output channel 176 c of thechip tester, the second unshared input 155 c of the first dut 150 c isconnected with a fourth output channel 177 c of the chip tester, thefirst unshared input 164 c of the second dut 160 c is connected with afifth output channel 178 c of the chip tester and the second unsharedinput 165 c of the second dut 160 c is connected with a sixth outputchannel 179 c of the chip tester.

To summarize, each of the duts 150 c, 160 c comprises at least 1 (in theexample: 2) shared inputs, wherein a shared input of the first dut 150 cand a shared input of the second dut 160 c are connected to the sameoutput channel of the chip tester. Outputs of the duts 150 c, 160 c areconnected individually to input channels of the chip tester. The inputchannels comprise respective tester receivers. In general, it should benoted that at least one output of the first dut 150 c is connected to aninput channel of the chip tester. Moreover, the duts 150 c, 160 ccomprise at least 1 (in the example: 2) unshared inputs, which areconnected individually to corresponding output channels of the chiptester. In other words, there is at least one output channel of the chiptester, which is cabled to an input of only one device under test out ofthe first device under test and the second device under test. Such anoutput channel of the chip tester in the following will also bedesignated as an unshared test channel. It should be noted that a firstunshared test channel of the chip tester is connected to an inputterminal of the first device under test 150 c but not to an inputterminal of the second device under test 160 c, and that a secondunshared test channel of the chip tester is connected to an inputterminal of the second device under test 160 c but not to an inputterminal of the first dut 150 c.

In the present document, a tester output channel is also brieflydesignated as tester driver. A tester input channel is brieflydesignated as tester receiver.

Moreover, it should be noted that the shared bus lines 170 c, 171 c areoptionally terminated. A termination of a shared bus line 170 c, 171 ccan, for example, comprise a termination resistance 180 c, 182 c.Moreover, the termination may optionally further comprise a terminationvoltage source 181 c, 183 c.

In the following, architectural impacts of driver sharing on a fixturedelay calibration will be described with reference to FIG. 2 c.

It should be noted here that, in an embodiment, the structures shown inFIGS. 2 a, 2 b and 2 c may be implemented on a device under test board(dut board), wherein the connections between the channels of the chiptester and the duts comprise transmission lines, routed on the dutboard, and electrical connectors adapted to provide an electricalconnection between the dut board and terminals of the duts. Electricalconnectors may, for example, be test sockets for providing a detachableelectrical connection. The electrical connectors may also comprise nailsor tips adapted to provide an electrical connection. However, any othertypes of connectors may be used. When driver sharing (i.e. connectinginput terminals of multiple duts to a single, shared output channel of achip tester) is implemented on a dut interface (or dut board), twocategories of device input pins or device input terminals may bedistinguished: input pins (or input terminals) connected to unsharedtester driver channels or unshared tester output channels (so-calledunshared dut inputs) and input pins (or input terminals) connected toshared tester driver channels or shared tester output channels(so-called shared dut inputs). In an embodiment, the receiver channelsare not shared. Unshared inputs of a device (or dut) are conventionalinput pins that are connected 1:1 to a tester driver channel or testeroutput channel. Assuming the so-called “daisy chain sharing”, sharedinputs of a device are connected to lines of a shared bus. In anembodiment, the shared inputs of a group of N devices are connected toone shared bus (or shared bus line). In an embodiment, each line of theshared bus is connected to one tester driver channel. Therefore, in anembodiment, one tester driver channel drives N shared inputs. In anotherembodiment, multiple shared buses may exist on a dut interface (or dutboard) to accommodate the parallel testing of M devices. A number K ofshared buses on an interface (or dut board) is, therefore, K=M/N. N isalso called “sharing factor”.

In an embodiment, the lines of a shared bus are operated as terminatedtransmission lines to achieve high speed. The N shared inputs connectedto one line of the bus form taps to the transmission line. Even thoughthe shared inputs are operated in a high impedance mode, in anembodiment of the invention (for example, with on-die termination offfor devices with on-die termination ODT on shared inputs) each inputcomes with a parasitic load which causes distortions on the signals thatpropagate along the shared bus. Therefore, in an embodiment of theinvention, when driver sharing is implemented to test memory devices,only the lower speed signals, such as command and control inputs, areoperated as shared inputs. However, the concept may also be used withother devices.

A driver sharing by−2 implementing the principle described above isillustrated in FIGS. 2 a, 2 b and 2 c.

According to an embodiment of the present invention, a dut interface ordut board that implements driver sharing for a memory device contains Ksocket boards for N devices on each board. Therefore, each of saidsocket boards implements one shared bus. Thus, the shared bus as well asunshared inputs of a device are connected to a mother board with cables(wherein the motherboard may provide the connection between the cablesand channel modules of the chip tester). Due to a high data rate of theduts and the relatively long signal path, a fixture delay calibration isperformed to compensate the propagation delays induced by the longsignal path on the interface (or dut board). However, the existence ofthe shared bus on the socket board (or dut board) has to be taken intoaccount when performing the fixture delay calibration. If, for example,the fixture delay for the first dut (DUT 1) is measured and stored forthe shared and unshared inputs of the dut and for the outputs of thedut, the fixture delay values for the driver channel driving the sharedbus are only valid for the first dut (DUT 1). In the above context, theterm “fixture delay value” may designate a propagation delay betweenchip tester ports (also designated as chip tester contact elements) ofthe dut board and dut terminals (or dut contact elements) of the dutboard. Alternatively, the term “fixture delay value” may also designatea total propagation delay between a chip tester channel port and a dutterminal (or dut contact element) of the dut board. However, for asecond device under test (DUT 2), an additional delay occurs caused bythe propagation delay of the signals on the shared bus from the firstdevice under test (DUT 1) to the second device under test (DUT 2).

However, it is not obligatory to use the fixture delay of the firstdevice. Alternatively the fixture delay of the second, third or N-thdevice could be used as well.

In an embodiment of a chip tester, only one fixture delay value ispossible for the driver channel driving the shared bus, and anadditional delay on the bus is compensated by other means.

In the following, a concept of compensating different propagation delayson a shared line will be described. For this purpose, reference is takento the architecture shown in FIG. 3. FIG. 3 shows a block schematicdiagram of a chip tester connected to two devices under test. The chiptester in FIG. 3 is designated in its entirety with 300. It should benoted that the chip tester 300 is similar to the chip tester 100 of theFIG. 1. For this reason, same means and signals are designated with thesame reference numerals and will not be explained here again. Instead,reference is taken to the description of the FIG. 1. However, the chiptester 300 also comprises a third channel 138. A third channel port 139is associated with the third channel 138. Moreover, it should be notedthat the second channel port 136 is in an embodiment connected with asecond terminal 154 of the first dut 150. Similarly, the third channelport 139 is connected with a second terminal 164 of the second dut 160.It should be noted that in an embodiment the first dut 150 is of thesame type as the second dut 160. In other words, the first dut 150 andthe second dut 160 may, for example, be two samples out of a set ofchips which are assumed to be identical under ideal circumstances.Moreover, it should be noted that the second channel 132 and the thirdchannel 138 may either both be input channels or may both be outputchannels. The definition “output channel” comprises an input/outputchannel configured (e.g. by means of software or by means of a hardwareswitch) to act as an output port. Similarly, the term “input channel”comprises an input/output channel configured to act as an input port.

Moreover, a propagation delay between a first channel port 134 and thefirst terminal 152 of the first dut 150 is designated with Δtp1. Apropagation delay between the first channel port 134 and a firstterminal 162 of the second dut 160 is designated with Δtp2. Apropagation delay between a second channel port 136 and the secondterminal 154 of the first duty 150 is designated Δt2. A propagationdelay between the third channel port 139 and the second terminal 164 ofthe second dut 160 is designated Δt3.

In the following, it will be assumed that the second dut terminal 154 ofthe first dut 150 and the second terminal 164 of the second dut 160 areinput terminals. Naturally, the duts 150, 160 may also comprise outputterminals, but the output terminals are not shown here for the sake ofsimplicity. Consequently, it is assumed that the second channel 132 andthe third channel 138 are driver channels. Moreover, it is assumed thatthe propagation delays Δtp1, Δtp2, Δt2, Δt3 are known to the chiptester. For example, the chip tester may be adapted to read a filecomprising said propagation delay values. Alternatively, the chip testermay, for example be adapted to perform a time domain reflection (TDR)measurement in order to determine said propagation delay values.However, in an embodiment of the present invention, the chip tester isadapted to primarily obtain a propagation delay difference information112. The propagation delay difference information 112 describes thedifference between the propagation delay Δtp2 and propagation delayΔtp1. Consequently, the timing calculator 110 calculates the timinginformation 114 defining the relative timing of the second channel 132and the third channel 138. A time shift between the timing of the secondchannel 132 and the third channel 138 is adjusted in dependency on thepropagation delay difference information 112. In other words, a relativetime shift between the signal outputs of the second channel 132 and thethird channel 138 is adjusted by taking into consideration thepropagation delay difference information, i.e. the difference Δtp2−Δtp1.However, the timing calculator 110 may in an alternative embodimentconsider further information, for example, the propagation delay valuesΔt2 and Δt3, when calculating timing information 140 for a relativetiming of the second channel 132 and the third channel 138. However, thepropagation delay values Δt2 and Δt3 may be neglected for thedetermination of a relative timing between the second channel and thethird channel if said propagation delay values are approximatelyidentical, which may, for example, be reached by an appropriate routingof the non-shared connections for the second terminal 154 of the firstdut 150 and the second terminal 164 of the second dut 160. Moreover, thetiming calculator 110 may optionally (but not necessarily) be adapted tocalculate a timing information for the first channel 130. By providingthe timing information for the channels 130, 132, 138, a specificrelative timing of the different input signals to the first dut 150 andthe second dut 160 can be adjusted.

FIGS. 4 a, 4 b and 4 c describe a setting of timings, which may be usedin an embodiment of the invention.

In the following, it will be assumed that the time reference t=0 is setto designate the time when the signals arrive at the first dut 150.However, this is naturally an arbitrary choice, and a different timereference could be chosen.

In an exemplary embodiment, all signals (e.g. edges or transitions)should arrive at the first dut 150 at a time t=0. Accordingly, thetester may send the corresponding signals earlier. As shown in FIG. 4 a,the tester may provide a signal transition at the first channel port 134at a time t=−Δtp1. As shown in FIG. 4 b, the tester may provide a signaltransition at the second channel port 136 at time t=−Δt2.

At the second dut 160, the signal from the shared driver 130 arrives att=Δtp2−Δtp1. In other words, the signal form the shared driver 130arrives at the second dut 160 later by a propagation delay difference(Δtp2−Δtp1) than it arrives at the first dut 150.

Normally, the chip tester would provide a signal (or signal transition)at the third channel 138 at t=−Δt3 to make it arrive at the second dut160 at time t=0. However, according to an embodiment of the invention,the signal provided by the third channel 138 is delayed by (Δtp2−Δtp1)to make it arrive at the same time as the shared signal from the shareddriver 130, namely at t=Δtp2−Δtp1.

FIG. 4 c shows the signals provided by the third channel 138.

A time difference between the signal provided by the first channel 130at the first channel port 134 and the signal provided by the secondchannel 132 at the second channel port 136 is

−Δt2+Δtp1.

A time difference between the signal provided by the third channel 138at the third channel port 139 and the signal provided by the secondchannel 132 at the second channel port 136 is

−((Δtp2+Δtp1)+Δt3−Δt2).

FIGS. 4 d, 4 e and 4 f describe another advantageous setting of thetimings. It should be noted here that in order to provide a sufficientsynchronism of the input signals of the first dut 150 and the second dut160, it is sufficient for the timing calculator to know the propagationdelay difference information 112, i.e. Δtp2−Δtp1. In a basic embodiment,the timing calculator 112 can then provide timing information 114, whichdirects the channel module configurator 120 to introduce a time shiftidentical to the propagation delay difference information between thetimings of the third channel 138 and the second channel 132. Thus, thetiming calculator 110 provides timing information to the channel moduleconfigurator 120 which results in a timing configuration of the thirdchannel 138 and the second channel 132, such that the third channel 138provides the same signal pattern as the second channel 132, wherein thesignal pattern provided by the third channel 138 is delayed with respectto the signal pattern provided by the second channel 132 by (Δtp2−Δtp1).This case is illustrated in FIG. 4 d. In an embodiment, the relationΔt2=Δt3 may be fulfilled. However, if the timing calculator 112 furtherreceives (optional) information about Δt2 and Δt3, the timing calculatormay provide the timing information 114 taking into consideration Δt2 andΔt3. In this case, a time shift between the signal patterns provided bythe second channel 132 and the third channel 138 is adjusted to

Δtp2−Δtp1+Δt2−Δt3.

In a more advanced embodiment, the timing calculator 110 mayadditionally be adapted to provide the timing information to set atiming relationship between the first channel 130 and the second channel132. For this setting, it is obligatory that the timing calculatorreceives an information about the propagation delay Δtp1 and thepropagation delay Δt2. However, it is worthwhile noting that byadjusting the relative timing of the second channel 132 and the thirdchannel 138 merely making use of the propagation delay differenceinformation Δtp2−Δtp1 (and, optionally, a propagation delay timeinformation Δt2−Δt3) the timing of the second channel 132 and the thirdchannel 138 can be adjusted such that both duts 150 and 160 receivecorresponding signals with the same timing relationship.

In an embodiment of the present invention, the timing calculator 110 isadapted to receive the propagation delay difference informationΔtp2−Δtp1, the propagation delay information Δtp1, the propagation delayinformation Δt2 and either information about Δt2−Δt3 or the informationΔt3 itself. Based on this information, the timing calculator 110 isadapted to set the timings of the three channels 130, 132, 138 as shownin FIG. 4 d. In other words, the timing calculator is adapted to providetiming information to delay the second channel 132 by Δtp1−Δt2 withrespect to the first channel 130. Moreover, and more importantly, thetiming calculator 110 is adapted to provide timing information 114 toadjust a timing of the third channel 138 and the second channel 132,such that the timing of the third channel is delayed with respect to thetiming of the second channel by Δtp2−Δtp1, or by Δtp2−Δtp1+Δt2−Δt3.

Such a setting of the timings of the channels 130, 132, 138 has theeffect that the wave forms output by the first channel and the secondchannel arrive simultaneously at the first dut 150 and that the waveforms output by the first channel and the third channel arrivesimultaneously at the second dut 160.

It should be noted here that the graphical representation of FIG. 4 ddescribes the wave forms output by the first channel 130, the secondchannel 132 and the third channel 138 as a function of time. An abscissa410 describes a time and ordinates 412, 414, 416 describe the respectivesignals in terms of arbitrary units. Timing shifts between the outputsignals of the first channel 130, the second channel 132 and the thirdchannel 138 are also shown in the graphical representation of FIG. 4 d.

FIG. 4 e shows a graphical representation of wave forms arriving at thefirst device under test 150 in response to the output wave forms of thefirst channel 130, the second channel 132 and the third channel 138shown in FIG. 4 d.

An abscissa 420 describes the time and ordinates 422, 424 describe thesignals present at the input terminals 152, 154 of the first dut 150 interms of arbitrary units.

It should be noted here that for the timing of the output signals of thefirst channel 130 and the second channel 132 as shown in FIG. 4 d, thecorresponding signals arrive at the input terminals 152, 154 of thefirst dut 150 simultaneously. In other words, the signals at the inputterminals 152, 154 of the first dut 150 are in a specific relativetiming relationship (here: simultaneous arrival).

Taking reference now to FIG. 4 f, the timing at the input terminals 162,164 of the second dut 160 will be described. An abscissa 430 describesthe time and ordinates 432, 434 describe the signals at the inputterminals 162, 164 at the second dut 160. It should be noted here thatfor the timing of the first channel 130 and the third channel 138 shownin FIG. 4 d, the signals at the input terminals 162, 164 of the seconddut 160 arrive simultaneously. In other words, the signals arriving atthe input terminals 162, 164 are in a specific relative timingrelationship (here: simultaneous arrival). However, it should be notedthat relative timing relationships between, on the one hand, the signalsat the input terminals of the first dut 150 and, on the other hand,between corresponding signals at the input terminals of the second dut160, are identical, provided that the relative timing relationshipbetween the second channel 132 and the third channel 138 are adjusted asdescribed above. In other words, if for example the first dut isconfigured to receive two edges on two different signals delayed withrespect to each other by a given time, the second dut will also receivetwo edges on two different signals delayed with respect to each other bythe same given time.

To summarize the above, it can be noted that, according to oneembodiment of the present invention, it is actually possible thatrelative timings of the signals arriving at two different duts areidentical, provided that a relative timing of two channels of the chiptesters (here: the second channel 132 and the third channel 138) isadjusted in dependence on the propagation delay difference information112 (here: Δtp2−Δtp1). Adjusting the relative timing of two channels,one of which provides and unshared signal to the first dut 150 and oneof which provides and unshared signal to an input terminal of the seconddut 160, taking into account the propagation delay differenceinformation about a difference of propagation delays on a shared lineconnected to both duts 150, 160 allows for an elimination of the impactof the propagation delay difference on the shared line. Consequently, arelative signal timing present at the first dut 150 is identical to arelative signal timing of signals present at the second dut 160. Thus,both duts 150, 160 are tested under identical (relative) timingconditions. For this reason, identical test results can be expected forthe first dut 150 and the second dut 160, provided the duts 150, 160 areidentical.

As a result, an embodiment of the present invention allows aquasi-simultaneous (i.e. almost simultaneous but shifted by Δtp2−Δtp1)testing of two devices making use of both shared inputs and unsharedinputs or unshared outputs. Even high speed devices can be tested makinguse of the inventive concept, according to an embodiment of the presentinvention.

Taking reference to FIGS. 4 d, 4 e and 4 f, a configuration has beendescribed in which the second channel and the third channel act asoutput channels or tester driver channels. However a similarconfiguration is also usable if the second channel 132 and the thirdchannel 138 act as input channels.

In the following, it is therefore assumed that the second terminal 154of the first dut 150 is an output terminal and that the second terminal164 of the second dut 160 is also an output terminal.

Moreover, in an embodiment, the timing of the second channel 132 and ofthe third channel 138 are adjusted by the channel module configurator120 in response to the timing information 140 provided by the timingcalculator 110. It should be noted that in an embodiment of the presentinvention, the timing of the third channel 138 is delayed with respectto a timing of the second channel 132 by Δtp2−Δtp1. In anotherembodiment, the timing of the third channel 138 is delayed with respectto the timing of the second channel 132 by Δtp2−Δtp1+Δt3−Δt2. In otherwords, the timing of the third channel 138 is delayed with respect tothe timing of the second channel on the basis of the propagation delaydifference information. An example timing of a corresponding chip testset up is shown in FIG. 5. In other words, FIG. 5 shows a graphicalrepresentation of signals and timings which may be present in the chiptester 300 of FIG. 3 according to an embodiment of the presentinvention. It is assumed here that the first channel 130 provides asignal wherein a signal transition arrives at the first channel port 134at time t1. The signal transition arrives at the first dut 150 at timet1+Δtp1 and at the second dut at time t1+Δtp2. Moreover, the secondchannel 132 is adapted to sample an output signal of the first dut 150at time t1+Δtp1+Δt2+tD. Similarly, the third channel 138 is configuredto sample a signal provided by the second dut 160 at the timet1+Δtp2+Δt3+tD. It should be noted here that the timing shift betweenthe second channel 132 and the third channel 138 has been configured bythe timing calculator 110 and the channel module configurator 120 on thebasis of the propagation delay difference information 112.

As a consequence, the second channel effectively determines a signal,which is present at the output 154 of the first dut 150 when a time tDhas elapsed after the transition of the input signal of the first dut150. Similarly, the third channel 138 evaluates a signal which ispresent at the output 164 of the second dut 160 when a time tD haselapsed after a transition of the input signal of the second dut 160.

In other words, the above described shift of the timings of the secondchannel 132 and the third channel 138 has the effect that correspondingoutput signals of the duts 150, 160 are sampled, occurring at identicalrelative timing positions with respect to the respective input signalsof the duts 150, 160.

Thus, the above described configuration of the second channel 132 andthe third channel 138 has the effect that identical duts 150, 160produce identical test results despite the propagation delay differenceΔtp2−Δtp1, even in a high speed test environment.

In the following, a concept will be described which allows theimplementation of the adjustment of the timings of multiple channels ina shared line test architecture, making use of a conventional fixturedelay calibration. In order to facilitate the understanding of anembodiment of the present invention, the concept of fixture delaycalibration will be outlined in the following.

Fixture delay calibration is a dedicated tool to compensate delays alonga signal path of an interface or a dut board (e.g. between a channelport of a tester channel and a dut terminal, or between a channel portof a tester channel and a dut connection element for connection of adut). For this reason, an embodiment of the present invention comprisesa concept (i.e. a method or an apparatus) that is based on the fixturedelay calibration.

An original purpose of the fixture delay calibration is to establish atiming reference (t=0) at dut contact elements (e.g. at pins of a DUTsocket). However, when driver sharing is implemented (e.g. when inputterminals of multiple duts are connected to a single chip tester outputchannel) this can be achieved only for one dut connected to a sharedbus. In other words, in an embodiment of the present invention, a timingreference of t=0 can only be established for one single dut out of aplurality of duts connected to a shared line.

However, it has been found that for testing devices on a shared bus, itis not obligatory to establish a timing reference with t=0 for all dutsindividually at the dut contact elements (e.g. at the pins of the devicesockets). Rather, according to an embodiment of the present invention,it is sufficient to just guarantee synchronism, which means that thestimulus of all inputs of one dut arrive at the same point in time(which may be different from zero) and that a compare action for one dutis performed relative to this point in time.

With this simplification, it is no longer needed to maintain severaldifferent fixture delay values for the shared inputs. Instead, it ispossible to use only one fixture delay value for each shared input ofall duts. However, the timing for the unshared input and the outputs ofeach individuals dut is, according to one embodiment, adapted such thatthey remain synchronized with the shared inputs. This is equivalent toestablishing one and the same timing reference for all duts connectedwith one shared bus at an arbitrary location. Therefore, the fixturedelay calibration can still be used to compensate the propagation delaycaused by the dut interface, even when driver sharing is implemented.According to an embodiment of the present invention, it is only neededthat the fixture delay values measured are modified to ensuresynchronism for all duts. This can be achieved by an additional toolperforming a post-processing on the fixture delay calibration files.

Regarding the fixture delay calibration, it should be noted that thechip tester, according to one embodiment of the present invention, isadapted to obtain information about a propagation delay between thechannel port of the tester and a terminal of a dut. If the chip testerobtains the information that there is a certain delay between a certainchannel port and a certain dut terminal, the chip tester configures thetiming of the respective chip tester channel accordingly. If the chiptester channel is an output channel, the chip tester will advance thetiming of the respective channel with respect to a reference timing inorder to compensate for the propagation delay. If the channel is aninput channel, the chip tester will delay the timing of the inputchannel with respect to a reference timing in order to compensate forthe propagation delay. It should be noted here that the reference timingmay, for example, be a timing under the assumption that there is nodelay present between the channel port and the dut terminal.

In the following, details of a proposed fixture delay calibration methodaccording to an embodiment of the present invention will be described.Firstly, a compensation of propagation delays according to an embodimentof the present invention will be described. When testing any devicesunder test (e.g. when testing memory devices) with driver sharing, afixture delay measurement is performed using a short circuit deviceinserted into a dut socket (or dut connection element) instead of anactual device. Subsequently, a time domain reflection measurement ismade by providing an excitation signal to a chip tester port (or chiptester connection element) of the dut board and by measuring a responsesignal at the dut port (or dut connection element). There are tworeasons for using a short (or short circuit device) for the measurementinstead of an open (or an open circuit). The first reason is the factthat the DQ lines (or shared lines, or data lines) are configured asdual transmission lines and that the location of the dut terminal (ordut pin or dut connection element) can only be identified with a shortat that point. The second reason is the fact that the shared bus alsobehaves like a dual transmission line when we look at it from theperspective of one dut.

Measuring the fixture delay values in the aforementioned way for adriver sharing interface (or a dut board), therefore, means to insert ashort circuit device into the first dut or dut socket, to measure thefixture delay and store it into a first file (file 1), then insert theshort circuit device into the second dut (dut 2) (or into a second dutsocket), to measure the fixture delay and store it into a second file(file 2). In an embodiment, the measurements are repeated, placing ashort circuit device into the different dut sockets subsequently, untila measurement of a N-th dut (DUT N) is stored in a N-th file (file N).The different fixture delay calibration files represent different delaysfor the shared inputs depending on which dut socket was loaded with theshort circuit device plus the delays of the unshared inputs and theoutputs that belong to the same dut.

However, it should be noted that it is not needed to save the results ofall the measurements into separate files. In contrast, a single file orany other appropriate data structure could be used.

According to an embodiment of the present invention, a way to compensatethe different signal paths for the individual duts on the shared bus ina single fixture delay file is as follows:

Start with the result of a conventional fixture delay calibration forall duts (or at least for a subset of duts of interest), stored in Nfixture delay calibration files (or in any other appropriate datastructure), wherein N is the sharing factor. According to an embodimentof the present invention, these files are supplied from the interfacemanufacturer who performs this measurement after manufacturing (theinterface or the dut board) using time domain reflection (TDR)equipment. However, the N fixture delay calibration files can also begenerated with a fixture delay calibration tool contained in the“SmarTest” software provided by the applicant.

The next step is to compensate the signal path to the first dut in aconventional way, leaving the fixture delay data of the first dut (DUT1) untouched.

The third step is to compensate the signal path to the other duts on theshared bus (DUT 2 . . . DUT N) by modifying the fixture delay values ofthe unshared inputs and the outputs.

Finally, the result is merged in a single fixture delay calibrationfile.

This approach effectively establishes a reference time (T=0) for allduts to the pins or dut contact elements of the first dut socket (or dutconnector) (DUT 1). When the reference time is chosen to be the timewhen the stimulus signals arrive at the shared inputs of the first dut,the same signals arrive at the second dut with an additional delay Δt12caused by a signal propagation from DUT 1 to DUT 2 (wherein therelationship Δt12=Δtp2−Δtp1 may hold).

It is, however, not needed that the reference T=0 is chosen to be at thepins of the first dut 150 (DUT1). Another embodiment could be to adjustthe reference T=0 to DUT2, DUT3 or DUT N, or to another arbitrary pointin time.

To ensure that the stimulus signals of the unshared inputs of DUT 2arrive at the same time as the stimulus signals of the shared inputs,the signals of the unshared inputs of DUT 2 have to be delayed by thesame amount Δt12. Since all input signals are now delayed by the sameamount relative to the arrival of the signal at DUT 1, the output of DUT2 will also be delayed by the same amount Δt12. Therefore, the compareaction taking place in the receiver channels has to be delayedaccordingly. When the delay Δt12 is achieved on the unshared inputs andthe outputs of DUT 2, a synchronism will also be guaranteed for DUT 2,and the device can be tested as usual.

The delay of the unshared input signals and the output signals can beachieved by the modification of the respective fixture delay calibrationvalues of each dut. This is possible because, in contrast to the sharedinputs, the unshared inputs and the outputs of each dut are connected toindividual tester channels. During a post-processing step, the measuredfixture delay values of the unshared inputs and the outputs are modifiedto account for the additional delay Δt12, relative to the first dut(Δt12, Δt13 . . . Δt1N if there are N devices on one shared bus).

In order to delay the signals on the unshared inputs by the amount ofΔt12, the respective fixture delay values have to be reduced by Δt12.The reduced fixture delay values have the consequence that the testerdrivers send their stimulus signals later, assuming that the shortersignal path has to be compensated. In order to delay the signals on thedut outputs, the respective fixture delay values have to be increased byΔt12. The increased fixture delay values have the consequence that thetester receivers perform their compare action later, assuming a longersignal path has to be compensated.

In an embodiment of the present invention, the above describedpost-processing first analyses the N fixture delay calibration files (orany other data structure, in which the respective propagation delayvalues are provided) and calculates the difference (or propagation delaydifference) between the second dut (DUT 2) and the first dut (DUT 1) foreach shared input. The delay Δt12 is obtained by averaging thedifferences on all shared inputs. Because of the averaging, in anembodiment of the present invention the lengths of the shared busbetween the second dut (DUT 2) and the first dut (DUT 1) are preciselylength matched. In the next step, the post-processing subtracts thevalue Δt12 from the fixture delay value of each unshared input of thesecond device (DUT 2). It further adds the value Δt12 to the fixturedelay value of each output of the second dut (DUT 2) and stores it as anew fixture delay value. The measured fixture delay values of the firstdut (DUT 1) are left unchanged. The fixture delay values used for theshared bus are those obtained from measuring the first dut (DUT 1). Thepost-processing finally combines the new and unchanged fixture delayvalues for all duts and stores it into a new fixture delay calibrationfile (or provides any other appropriate data structure). If there are Ndevices on the shared bus, the procedure is applied for all duts fromthe second dut (DUT 2) to the N-th dut (DUT N) (i.e. the procedure isapplied to DUT 2, DUT 3, . . . DUT N), processing the respective delaysΔt12, Δt13, . . . Δt1N in the same way for each dut.

For a typical interface, the values measured for the unshared inputsduring fixture delay calibration are dominated by the propagation delayof a cable connecting a socket board (or dut board) with themotherboard. When these values are reduced during post-processing toaccount for the delay between the first dut (DUT 1) and the N-th dut(DUT N) on the shared bus, the result is typically positive, since thedelays on the cables are typically larger than the delays on the tracesof the shared board. However, when large sharing factors N areimplemented, the delay on the shared bus may exceed the delay on thecable and a negative value may be the result of the post-processing. Inthis case, an additional offset can optionally be added to the fixturedelay values of all inputs and subtracted from the fixture delay valuesof all outputs before applying the above modification procedure.

The consequence of using an additional offset is just a change of thereference time without affecting the synchronism.

When K shared buses are implemented on an interface to test M=K*Ndevices in parallel, a conventional fixture delay calibration and theabove described post-processing sequence can be performed for the Kbuses in parallel using K short circuit devices. This means that thefirst dut (DUT 1) of all shared buses is measured first, followed by thesecond dut (DUT 2) to the N-th dut (DUT N). Again, N fixture delaycalibration files are generated containing the measurement data of all Kbuses. However, any other appropriate data structure may be generated.During post-processing, Δt12 for all K buses is processed in a firststep, followed by Δt13 . . . ΔtN. The result of the post-processing isone new fixture delay calibration file, valid for a whole interface (orfor a whole dut board). However, any other appropriate data structuremay be created.

The above described post-processing and merging of the N fixture delaycalibration files into one fixture delay calibration file valid for adriver sharing interface is currently performed by a script based UNIXtool provided with a “HSM 3600” software. Alternatively, any othersoftware or hardware can be used for the post processing.

In the following, the general concept of an apparatus forpost-processing an original propagation delay value will be described.For this purpose, FIG. 6 shows a block schematic diagram of an apparatusfor post-processing an original propagation delay value, according to anembodiment of the present invention. The apparatus of FIG. 6 isdesignated in its entirety with 600. The apparatus 600 is adapted topost-process a plurality of propagation delay values of a dut interface(or dut board) for a chip tester.

It is assumed here, that the dut interface (or dut board) is adapted toprovide an electrical connection between a chip tester and at least twoduts, and that the dut board comprises a first dut contact element forproviding a detachable electrical contact between the dut board and afirst dut, a second dut contact element for providing a detachableelectrical contact between the dut board and the second dut, a third dutcontact element for providing a detachable electrical contact betweenthe dut board and the first dut and a fourth dut contact element forproviding a detachable electrical connection between the dut board thesecond dut. Moreover, it is assumed that the dut board comprises a firstchip tester contact element for providing a detachable electricalcontact between the dut board and a chip tester. Moreover, it is assumedthat the dut board comprises a second chip tester contact element forproviding a detachable electrical contact between the dut board and thechip tester, and a third chip tester contact element for providing adetachable electrical contact between the dut board and the chip tester.Moreover, it is assumed that the first dut contact element and thesecond dut contact element are both electrically connected to the firstchip tester contact element. The third dut contact element iselectrically connected to the second chip tester contact element, andthe fourth dut contact element is electrically connected to the thirdchip tester contact element. Details regarding a possible dut interfaceconfiguration are shown in FIGS. 7 a to 7 c.

It should be noted that in the present description, a dut board isdescribed as an example of a dut interface. However, other types of dutinterfaces for providing a connection between the chip tester and one ormore duts can be used.

The apparatus 600 comprises a propagation delay determinator 610, whichis adapted to obtain an original (or actual) propagation delay valuedescribing a propagation delay between the fourth dut contact elementand the third chip tester contact element. The propagation delaydeterminator 610 is adapted to provide the obtained propagation delayvalue as an original propagation delay value 612. Moreover, theapparatus 600 comprises a propagation delay difference valuedeterminator 620, which is adapted to obtain and provide a propagationdelay difference 622, describing a difference between, on the one hand,a propagation delay between the first chip tester contact element andthe first dut contact element, and, on the other hand, a propagationdelay between the first chip tester contact element and the second dutcontact element. Moreover, the apparatus 600 comprises a propagationdelay modifier 630, which is adapted to modify the original propagationdelay value 612 using the propagation delay difference value 622.Consequently, the propagation delay modifier 630 is adapted to provide amodified effective propogation delay value 632.

In an embodiment of the invention, the modified effective propagationdelay value 622 may take the place of the original propagation value612. In an other embodiment of the present invention, the modifiedeffective propagation delay value 622 may, for example, be used as thetiming information 140, which serves as an input information for thechannel module configurator 120 in the chip tester 100. It should alsobe noted that the apparatus 600 can be considered to make up the timingcalculator 110 of the chip tester 100.

Moreover, it should be noted that in an embodiment, the apparatus 600 isadapted to produce a data structure (for example, a file) on the basisof one or more modified effective propagation delay values 632.Moreover, the apparatus 600 may, in an embodiment, be adapted to processas an input information one or more of the above-described fixture delaycalibration files and to produce a new fixture delay calibration file(which may also be designated as a modified fixture delay calibrationfile, or an effective fixture delay calibration file) on the basis ofone or more of the modified effective propagation delay values.

In the following, a typical dut board and a corresponding dut boardpropagation delay data structure will be described. Subsequently, aprocessed modified (or effective) dut board propagation delay datastructures will be shown. FIG. 7 a shows an example of a dut board for adriver sharing test of at least two duts. The dut board of FIG. 7 a isdesignated in its entirety with 700. Moreover, FIG. 7 a shows graphicalrepresentations of two possible dut board propagation delay datastructures, which are designated with 720 and 730. The dut board 700comprises 3 chip tester contact elements 702, 704, 706. The chip testercontact elements (or chip tester connectors or chip tester ports) areadapted to provide an electrical connection between the chip tester andthe dut board 700. The chip tester contact elements may, for example, becontact elements, which are adapted to interact with a POGO interface ofa chip tester. Moreover, the dut board 700 comprises 4 dut contactelements 710, 711, 712, 713. The dut contact elements are adapted toprovide an electrical contact between the dut board 700 and two duts. Inparticular, the first dut contact element 710 and the third dut contactelement 712 are adapted to provide electrical contacts with twodifferent terminals of a first dut, and the second dut contact element711 and the fourth dut contact element 713 are adapted to provide anelectrical contact to two different terminals of a second dut.

The first and third dut contact elements 710, 712 may, for example, be apart of a first dut socket for the first dut, and the second and fourthdut contact elements 711, 713 may, for example, be part of a second dutsocket for a second dut.

Moreover, the first and second dut contact elements 710, 711 areelectrically connected to the first chip tester contact element 702 viaa shared line. In other words, the first dut contact element 710 and thesecond dut contact element 711 are both connected to the same chiptester contact element. The connection is performed by a transmissionline on the dut board. Moreover, the third dut contact element 712 iselectrically connected to the second chip tester contact element 704,and the fourth dut contact element 713 is electrically connected to thethird chip tester contact element 706.

Further, an original data structure (e.g. an original file) exists,which describes physical characteristics of the dut board 700. Forexample, the data structure may comprise the information as shown forthe file 720. In particular, the original data structure or file maycomprise an information about a propagation delay between the first chiptester contact element 702 and the first dut contact element 710, whichis designated with Δtp1. Moreover, the original data structure maycomprise information about a propagation delay between the first chiptester contact element 702 and the second dut contact element 711, whichis designated with Δtp2. The original data structure may furthercomprise information about a propagation delay between the third dutcontact element 712 and the second chip tester contact element 704designated with Δt2, and an information about a propagation delaybetween the fourth dut contact element 713 and the third chip testercontact element 706 designated with Δt3. Alternatively, the informationregarding the first dut (namely Δtp1, Δt2) and the information regardingthe second dut (namely Δtp2, Δt3) may be comprised in separate datastructures or separate files, as shown at reference numeral 730.

However, in an embodiment of the present invention, a modified datastructure comprising modified (or effective) propagation delay values isprovided with the dut board. The dut board and the modified datastructure may be considered to be a dut board set or test fixture set.In an embodiment of the present invention, the modified data structure(or modified file) comprises an information about the propagation delaybetween the first chip tester contact element 702 and the first dutcontact element 710, for example, the value Δtp1. Moreover, the modifieddata structure comprises an information about the propagation delaybetween the third dut contact elements 712 and the second chip testercontact element 704, for example, the value Δt2. Additionally, themodified data structure comprises a modified (or effective) informationabout a propagation delay between the forth dut contact elements 713 andthe third chip tester contact element 706. Said amended or effectivepropagation delay value is, in an embodiment of the present invention,based on the actual propagation delay value Δt3 and amended on the basisof a propagation delay difference information describing a difference ofpropagation delays between, on the one hand, the first chip testercontact element 702 and the first dut contact element 710 and, on theother hand, the first chip tester contact element 702 and the second dutcontact element 711. For example, the modified propagation delay valuemay be computed as

Δt3−(Δtp2−Δtp1).

However, an alternative computation method may be used. According to ageneral embodiment of the present invention, the original propagationdelay values between the third dut contact element and the second chiptester contact element (Δt2), and between the fourth dut contact elementand the third chip tester contact element (Δt3) are modified in such away that a difference between the amended (or effective) propagationdelay values (Δt3,effective−Δt2,effective) deviates from a differencebetween the original propagation values (Δt3−Δt2) by the propagationdelay difference for the shared line (Δtp2−Δtp1).

In other words:

Δt3,effective−Δt2,effective=Δt3−Δt2+Δtp2−Δtp1.

For example, the following relations may hold:

Δt2,effective=Δt2

Δt3,effective=Δt3−(Δtp2−Δtp1)

Δt3,effective−Δt2,effective=(Δt3−Δt2)−(Δtp2−Δtp1).

Alternatively, the following relations may hold:

Δt2,effective=Δt2

Δt3,effective=Δt3+(Δtp2−Δtp1)

Δt3,effective−Δt2,effective=(Δt3−Δt2)+(Δtp2−Δtp1).

The amended or effective propagation delay values may be comprised inone or more data structures. Exemplary data structures are shown in FIG.7 b, describing an effective dut board 740. In an embodiment of thepresent invention, an amended data structure (or effective datastructure) may, for example, comprise the propagation delay value Δtp1,the propagation delay value Δt2,effective and the propagation delayvalue Δt3,effective. As described above, the following relations mayhold in an embodiment of the present invention:

Δt2,effective=Δt2;

Δt3,effective=Δt3−(Δtp2−Δtp1)

In an alternative embodiment, two data structures or two separate filesmay be provided, a first file comprising the propagation delay valuesΔtp1 and Δtp2,effective and the second file comprising the propagationdelay values Δtp1 and Δt3,effective.

It should be noted here that the amended propagation delay datastructures described with reference to FIG. 7 b may, for example, beapplied if the dut contact element 712, 713 are intended to be connectedto input ports of a dut.

In the following, an alternative amended data structure, or effectivedata structure characterizing a dut board will be described, takingreference to FIG. 7 c. For this purpose, FIG. 7 c shows a graphicalrepresentation of an effective dut board and of a corresponding datastructures characterizing the effective dut board.

It should be noted here that the data structures described withreference to FIG. 7 c is similar to the data structure described withreference to FIG. 7 b. However, the effective propagation delayΔt3,effective between the third chip tester contact element and thefourth dut contact element is chosen to be

Δt3+(Δtp2−Δtp1)

It should be noted that, according to an embodiment of the presentinvention, the data structure described with reference to FIG. 7 c may,for example, be used if the third dut contact element and the fourth dutcontact element are intended to be connected to output ports of twoduts.

FIG. 7 d shows an example of an extended configuration for testing twoduts. The configuration of FIG. 7 d comprises a first dut 790 and asecond dut 792. An input 790 a of the first dut 790 and an input 792 aof the second dut 792 may be configured to be shared inputs. Said inputs790 a, 792 a of the first and second dut 790, 792 may therefore beconnected to a shared output of the chip tester. Moreover the first dut790 may comprise at least one unshared input 790 b and at least oneunshared output 790 c. The second dut 792 may also comprise at least onunshared input 792 b and at least one unshared output 792 c.

In other words, in an embodiment, a device has shared inputs, unsharedinputs and unshared outputs.

In many test situations, there is more than one shared line. In thiscase, the timing delay calculator 110 or the propagation delaydifference value determinator 720 may be adapted to obtain aninformation about a difference in propagation delay to different sharedinputs of the device under test by performing an averaging. This conceptwill subsequently be described taking reference to FIG. 8, which shows ablock schematic diagram of a test environment comprising at least twoduts, each of which comprises at least two shared inputs. The testenvironment of FIG. 8 is designated in its entirety with 800. A firstdut is designated with 810 and a second dut is designated with 820. Thefirst dut 810 comprises a first shared input 812 and a second sharedinput 814. Moreover, the first dut 812 comprises an additional input oroutput 816. The second dut 820 comprises a corresponding first sharedinput 822, a second shared input 824 and another input or output 826.The first shared input 812 of the first dut and the first shared input822 of the second dut are both connected to a shared, bus-liketransmission line 830. The second shared input 814 of the first dut andthe second shared input 824 of the second dut are both connected to asecond shared, bus-like transmission line 832. The first sharedtransmission line 830 comprises a chip tester contact element 834, andthe second shared transmission line 832 comprises a corresponding chiptester contact element 836. The propagation delay between the chiptester contact element 834 and the first shared input 812 is designatedwith Δtp1,1. The propagation delay between the chip tester contactelement 834 and the first shared input 822 of the second dut isdesignated with Δtp1,2. The propagation delay between the chip testercontact element 836 and the second shared input 814 is designated withΔtp2,1 and a propagation delay between the second chip tester contactelement 836 and the second shared input 824 is designated with Δtp2,2.Consequently, the propagation delay difference value Δtp1,2−Δtp1,1 forthe first shared transmission line can be determined. Similarly, apropagation delay difference value Δtp2,2−Δtp2,1 for the second sharedtransmission line can be determined. For the further computations, forexample, for the calculation of the timing information 114 or for thecomputation of amended data structures, an average value can be used,which can be obtained by averaging the propagation delay differencevalues for individual transmission lines.

An averaging formula, which can be supplemented by propagation delaydifference values for further shared transmission lines, if desired, isgiven in FIG. 8.

FIG. 9 shows a graphical representation of a test fixture set, accordingto an embodiment of the present invention. The test fixture set isdesignated in its entirety with 900. The text fixture set 900 comprisesa dut board 910, which may be identical to the dut board 700, describedwith reference to FIG. 7 a. For this reason, reference is taken to theabove description.

The test fixture set 900 further comprises a data exchange medium ordata carrier 920 comprising the amended (or effective) propagation delayinformation, as described, for example, with reference to FIGS. 7 b and7 c. In other words, the data exchange medium or data carrier 920 mayrepresent one or more of the data structures or files described withreference to FIGS. 7 b and 7 c. In other words, the data exchange mediumor data carrier may comprise an amended or effective propagation delayvalue for at least one of the transmission lines of the dut board 910.Thus, the data exchange medium or data carrier 920 corresponds to thedut board 910. However, the data exchange medium 920 does not, or doesnot only, comprise actual or physical information about the propagationdelays of the transmission lines of the dut board 910, but also (orexclusively) comprises amended (or effective) propagation delay values,the generation of which was, for example, described with reference toFIGS. 7 b and 7 c.

The data exchange medium 920 may, for example, be a harddisk, floppydisc, a CD ROM, a DVD, a ROM, a PROM, a EPROM, a EEPROM or a /memorycomprising said amended propagation delay values. However, the dataexchange medium or data carrier may also be any other volatile ornon-volatile data carrier comprising said amended propagation delayvalues.

Moreover, a data packet adapted to be transported via a data transportnetwork is also considered to be a data carrier or a data exchangemedium. Thus, the test fixture set may also take the form of a physicaldut board and an online transmission of the corresponding amendedpropagation delay values.

In the following, a concept will be described, which allows for acompensation of device loading effects. The concept for the compensationof the device loading effects may optionally be applied in combinationwith the above described concept for adjusting timings of chip testerchannels. However, the concept for a compensation of device loadingeffects described in the following can also be used independent from theabove described approach.

For the following considerations, it is assumed that at least two dutsare connected to at least one shared line. However, in order tofacilitate the understanding, FIG. 10 shows a test setup comprising 4duts. The sharing factor is N=4. In other words, FIG. 10 shows a blockschematic diagram of a test set up comprising 4 duts. Also, FIG. 10shows propagation delays on a shared bus for a by−4 sharing. The testset up in FIG. 10 is designated in its entirety with 1000. The test setup 1000 comprises 4 duts 1010, 1012, 1014, 1016. Each of the dutscomprises, for example, three shared inputs designated with 1010 a, 1010b, 1010 c, 1012 a, 1012 b, 1012 c, 1014 a, 1014 b, 1014 c, 1016 a, 1016b, 1016 c. Shared inputs 1010 a, 1012 a, 1014 a, 1016 a are allconnected to a first shared line 1020 a, which is driven by a firstchannel 1022 a of a chip tester. Shared inputs 1010 b, 1012 b, 1014 b,1016 b are all connected to a shared line 1020 b, which is driven by asecond channel 1022 b of the chip tester. Shared inputs 1010 c, 1012 c,1014 c, 1016 c are all connected to a third shared line 1020 c, which isdriven by a third channel 1022 c of the chip tester.

Moreover, it should be noted that in an embodiment of the presentinvention the shared transmission lines 1020 a, 1020 b, 1020 c are(optionally) terminated by transmission line terminations 1024 a, 1024b, 1024 c.

Moreover, it should be noted that the shared transmission lines arelength-matched in an embodiment of the invention. The sharedtransmission lines comprise branch points (e.g. branch points 1030 a,1030 b, 1030 c), at which individual dut transmission lines branch fromthe shared transmission lines. It should be noted here that the lengthof the shared transmission lines between corresponding branch points are(at least approximately) identical. For example, a length of a segmentof the first transmission line 1020 a between the branch point 1030 aand the branch point 1032 a is, at least approximately, identical to thelength of a segment of the second transmission line 1020 b between thebranch point 1030 b and the branch point 1032 b. Consequently, apropagation delay between the branch point 1030 a and the branch point1032 a is, at least approximately, identical to a propagation delaybetween the branch point 1030 b and the branch point 1032 b, and alsoidentical to the propagation delay between the branch points 1030 c and1032 c. However, the length L₂₃ may be different from the length L₁₂.Also, the length L₃₄ my be different from the length L₂₃. In anotherembodiment, lengths L₁₂, L₂₃ and L₃₄ may be at least approximatelyidentical.

In the following, the motivation for a compensation of device loadingeffects will be described, before the technical solution will bepresented.

When duts (e.g. memory devices) are tested based on a fixture delaycalibration that just compensates the propagation delays of the signalpaths including the shared bus as described above, it becomes visiblethat the timing related results of some measurements, for example, theset up and hold times, still depend on the position of the dut on theshared bus. Further, different measurement results are obtained whensome dut sockets on the shared bus are not loaded with devices. Thereason for this dependency is that the delay of the signals on theshared bus is not only caused by the limited propagation velocity on thesocket board traces (or dut board traces), but also by a parasitic loadof duts connected to the shared bus. The loading is dominated by aninput capacitance of the shared inputs and causes a distortion of thesignals that includes certain delays of the signal transitions. In orderto make accurate measurements on a driver sharing interface, the deviceloading effect may be taken into account. An influence of the deviceloading on the total signal delay on the shared bus can, for example, beincluded into the fixture delay calibration. To achieve this, thefixture delay calibration can be performed with a short circuit deviceinserted in one dut socket and the dut sockets preceeding the shortedcircuit loaded with regular devices. Performing a fixture delaycalibration with devices loaded up to the short circuit device yields asecond set of N fixture delay calibration files with significantlylarger values for the shared inputs of DUT 2, . . . DUT N.

To extract an effect of the device loading, the values measured withdevices may be subtracted from the values measured without devices.

For DUT 2, the additional load is caused by DUT 1 only, whereas for DUTN, the additional load is caused by DUT 1, . . . DUT (N−1). The loadingeffect increases from DUT 2 to DUT N for each additional dut.

Assuming that the loading effect per dut is constant, the increase withthe dut number is linear. DUT 1 shows the same results with and withoutdevices, because there are no preceding devices (i.e. devices locatedcloser to the chip tester channel than DUT 1) to the dut measured. Thisallows a simplification of the extraction procedure for the loadingeffect per dut. It is sufficient that only the fixture delay measurementfor DUT N is performed with devices loaded into the circuits of DUT 1 toDUT (N−1). The loading effect per dut is designated with t_(L) and canbe determined from the following formula:

t _(L)=(Δt _(1N)[with devices]−Δt _(1N))/(N−1).

To calculate Δt_(1N) [with devices], the fixture delay values for DUT 1(e.g. Δtp1) can be taken from the measurement without devices becausethere is no difference. It is also sufficient to determine a loadingeffect per dut from only one shared bus (or from one socket board or dutboard).

As soon as the loading effect per dut is determined, the values Δt_(1n)[with devices] for all n=2, . . . , (N−1) can be calculated from:

Δt _(1n)[with devices]=Δt_(1n)+(n−1)*t _(L), for n=2, . . . , N−1.

Finally, the values Δt_(1n) [with devices] are used instead of Δt_(1n)during the post-processing that is performed to generate the finalfixture delay calibration file, valid for the whole interface.

In an embodiment, the following relations may be fulfilled:

Δt₁₂ =Δt _(p2) −Δt _(p1) und

Δt _(1N) =Δt _(pN) −Δt _(p1).

In another embodiment, the value t_(L) for the loading effect can beobtained from a simulation, or from some other calculation.

In the following, the above described algorithm for obtaining deviceload compensated propagation delay values will be summarized, takingreference to FIG. 11. For this purpose, FIG. 11 shows a flow chart of aninventive method for performing measurements in preparation of a deviceload compensation. The method of FIG. 11 is designated in its entiretywith 1100. A first step 1110 comprises determining a propagation delayΔtp1 for a first dut (i.e. a propagation delay between a chip testercontact element of the dut board a dut contact element of the dut boardfor the first dut). It should be noted here that the numbering of theduts (1st dut, 2nd dut, is chosen such that a lower number of dutindicates that the propagation delay between the chip tester contactelement of the dut board and the dut, or between the chip tester channeland the dut, is smaller.

In a second step 1112, an unloaded propagation delay for a second dut(with index n>1) is determined. For this purpose, a dut socket for thefirst dut is left open, and a short circuit element is placed in the dutsocket of the second dut. Consequently, the propagation delay Δtp2 ismeasured, for example, by performing a time domain reflectionmeasurement.

In a third step 1114, an unloaded propagation delay for the third dut isdetermined. For this purpose, a dut socket of the first dut and thesecond dut are left open, and a short circuit element is placed in thedut socket for the third dut. Consequently, the propagation delay Δtp3is measured, for example, by making a time domain reflectionmeasurement.

Naturally, the measurement can optionally be extended to cover more thanthree duts.

It should be noted that the order, in which the first step 1110, thesecond step 1112 and the third step 1114 are executed can be chosenarbitrarily. However, it should also be noted that the first step 1110,the second step 1112 and the third step 1114 can already be performedbefore a dut is available, and even before it is known which load anactual dut presents to the shared lines. It should also be noted thataccording to one embodiment of the present invention, the steps 1110,1112, 1114 are executed by the manufacturer of a dut board.

In a fourth step 1120, a propagation delay value is determined in aloaded state of the dut board. For this purpose, a dut or an equivalentload device, which presents a load to the shared lines that isapproximately identical to the load presented by the dut, is placed inat least one dut socket. Moreover, a short circuit device is placed in ahigher number dut socket. Thus, there is at least one dut or load deviceplaced in a socket (electrically) between the chip tester connectionelement of the dut board and the dut socket in which the short circuitdevice is placed. In an embodiment, all the sockets between the chiptester contact element and the dut socket with the short circuit deviceare loaded with duts or load devices, but this is not obligatory.Rather, it is sufficient if at least one dut or load device is used.

Consequently, the propagation delay Δt13 in a loaded state can bedetermined by, for example, making a time domain reflection measurement.

Moreover, it should be noted that a propagation delay contribution perdut (or per load) can, for example, be obtained by comparing results ofpropagation delay measurements for the same dut position in an unloadedstate and in a loaded state of other dut positions, taking intoconsideration how many duts or loaded devices have been effective insaid measurements.

Also, it should be noted that, according to an embodiment of the presentinvention, only one single propagation delay measurement in a loadedstate is needed in order to obtain loaded state propagation delays fordifferent device positions and/or different load states.

For example, if there are N dut positions, the propagation delaymeasurement in a loaded state only needs to be made for one single loadsituation to determine a propagation delay contribution per dut. Loadedstate propagation delays for other load situations can then becalculated by means of interpolating or extrapolating, assuming thateach dut increases linearly a propagation delay.

Moreover, propagation delays for various load states can be calculated.For example, a propagation delay can be calculated for a situation wherethe first dut and the third dut are placed on a dut board, but wherein asecond dut socket is left open. Accordingly, different load states canconsequently be handled without taking a measurement for each singleload state. In other words, according to an embodiment of the presentinvention, a propagation delay can be calculated for a load situation,in which at least one dut socket is unloaded, based on the assumptionthat each loaded dut socket contributes a certain pre-determinedpropagation delay, and further based on the assumption that an unloadeddut socket does not provide a contribution to the propagation delay.

Moreover, it should be noted that, in an embodiment of the presentinvention, a reconfiguration of the timing of the chip tester channelsmay be performed in response to a change of a loading state of the dutsockets. For example, during a test of a plurality of duts in amulti-socket arrangement with shared lines, it may be found that aspecific dut socket brings along a particularly high failure rate. Inthis case, it may, for example, be assumed that the specific socket isdefective. Therefore, it may be decided not to place any more duts inthe specific dut socket. Accordingly, after the decision not to load thespecific dut socket with duts, subsequent testing is performed in a loadconfiguration wherein at least one of the dut sockets is unloaded. Inother words, the decision not to load the specific dut socket bringsalong a change of the dut loading of the shared line. Consequently, itis expected that a timing change occurs, as the loading of the dutsocket has an impact on the timing of signals arriving at dut socketsbehind the unloaded specific dut socket. Consequently, in an embodimentof the present invention, a timing of the chip tester channels or atleast of one chip tester channel, may be recomputed in response to thedecision to change a loading state of a specific dut socket. The changeof the timing of the chip tester channel is performed such as tocompensate for the timing change due to the change of the load state.

The above mechanism can be summarized as follows:

A common strategy of semiconductor manufacturers who perform multi-sitetesting is the disabling of sites that permanently fail. If a site isdisabled, it will no longer be loaded from a device handler and, thus,does no longer show a loading effect. The consequence of this strategyis that the calculation of the Δt_(1i) [with devices] should take careof disabled sites. The handler communicates the disabling of sites tothe tester, therefore, this information is available. However, sincethis information is created dynamically during run time of the test,whereas the fixture delay calibration data are loaded statically at thebeginning of a test flow, the test may have to be paused while thefixture delay calibration data are updated. However, it may be expectedthat the above described strategy will bring along a reduction withrespect to test time.

FIG. 12 shows a flow chart of an inventive method for providing a timinginformation for adjusting a timing of a chip tester. In an embodiment ofthe present invention, it is assumed that the chip tester operates in aconfiguration, in which at least a first terminal of a first dut and afirst terminal of a second dut are connected to a first channel of thechip tester via a shared line. Moreover, it is assumed that a secondterminal of the first dut is connected to a second channel of the chiptester via an unshared line and that a second terminal of the second dutis connected to a third channel of the chip tester via an unshared line.The method 1200 of FIG. 12 comprises a first step 1210 of obtaining apropagation delay difference information describing a propagation timedifference between, on the one hand, a propagation delay from a firstchannel port of the chip tester to the first terminal of the first dutand, on the other hand, a propagation delay from the first channel portof the chip tester to the first terminal of the second dut. The method1200 comprises a second step of providing a timing information to adjusta timing shift between timings of a second channel of the chip testerand a third channel of the chip tester on the basis of the propagationtime difference information.

It should be noted that the method 1200 of FIG. 12 may be supplementedby any of the functionalities described with respect to the other meansand methods herein. Moreover, the present invention comprises a computerprogram for performing any of the methods described herein.

Depending on certain implementation requirements of the inventivemethods, the inventive methods can be implemented in hardware or insoftware. The implementation can be performed using a digital storagemedium, in for example a hard disk, floppy disk, a DVD a CD, a ROM, aPROM, an EPROM, an EEPROM or a FLASH memory having electronicallyreadable control signals stored thereon, which cooperate with aprogrammable computer system such that the inventive method isperformed. Generally, the present invention is, therefore, a computerprogram product with a program code stored on a machine readablecarrier, the program code being operative for performing the inventivemethod when the computer program product runs on a computer. In otherwords, the inventive method is, therefore, a computer program having aprogram code for performing the inventive method when the computerprogram runs on a computer.

In the following section, a possible implementation of an algorithm forthe fixture delay calibration for driver sharing will be described withpseudo-code. It should be noted that the generation of the fixture delaycalibration files as described in the procedurefixture_delay_calibration( ) is done, according to an embodiment of thepresent invention, by the interface manufacturer. The fixture delaycalibration files fd[1:N]are, according to an embodiment of theinvention, supplied along with the interface.

The algorithm can be described by the following routines, wherein theexpression “//” designates a comment, wherein a loop to be repeated fora plurality of values is described by “loop for . . . end loop”.Moreover, loops are further illustrated by indenting instructions withina loop.

  Fixture_Delay_Calibration ( N = number of DUTs per shared bus K =number of shared buses per interface) { //Analyze pin configurationDetermine P = number of pins per DUT Loop for n = 1 to N  Insert K shortcircuit devices into socket of DUT[n,1:K]  Create fixture delaycalibration file fd[n] for     DUT [n,1:K]  Loop for k = 1 to K   Loopfor p = 1 to P    Measure fixture delay fxdl_val[n,k,p] of pin[p] of     bus[k] and DUT[n,k]   End loop p  End loop k  Store fixture delayvalues fxdl_val[n,1:K,1:P] to file     fd[n] End loop n }Post_Processing_Procedure( N = number of DUTs per shared bus K = numberof shared buses per interface fd[1:N] = fixture delay calibration filesfrom     DUT[1:N,1:K]) { //Analyze pin configuration Determine SI =number of shared input per DUT Determine UI = number of unshared inputsper DUT Determine OP = number of outputs per DUT Create new fixturedelay calibration file fd_merge for the     whole interface //processDUT[1,1:K] data without compensation Open fixture delay calibration filefd[1] of DUT[1,1:K] Loop for k = 1 to K  Loop for si = 1 to SI   Readfixture delay value of shared input      si_fxdl_val[1,k,si] from fd[1]  Write fixture delay value of shared input      si_fxdl_val[1,k,si] tofd_merge  End loop si  Loop for ui = 1 to UI   Read fixture delay valueof shared input      ui_fxdl_val[1,k,ui] from fd[1]   Write fixturedelay value of shared input      ui_fxdl_val[1,k,ui] to fd_merge  Endloop ui  Loop for op = 1 to OP   Read fixture delay value of outputop_fxdl_val[1,k,op]      from fd[1]   Write fixture delay value ofoutput op_fxdl_val[1,k,op]      to fd_merge  End loop op End loop k//perform compensation for DUT[2:N,1:K] on unshared inputs     andoutput pins Loop for n = 2 to N  Open fixture delay calibration filefd[n] of DUT[n,1:K]  Loop for k = 1 to K   // calculate compensationvalue   Loop for si = 1 to SI    Read fixture delay value of sharedinput      si_fxdl_val[n,k,si] from fd[n]    Si_delta_t[n,k,si] =si_fxdl_val[n,k,si] −      si_fxdl_val[1,k,si]   End loop si  Delta_t1[n,k]= average over si (Si_delta_t[n,k,si])   // compensateunshared inputs   Loop for ui = 1 to UI    Read fixture delay value ofunshared input      ui_fxdl_val[n,k,ui]    New_ui_fxdl_val[n,k,ui] =ui_fxdl_val[n,k,ui] −      Delta_t1[n,k]    Write new fixture delay dataof unshared input      New_ui_fxdl_val[n,k,ui] to fd_merge   End loop ui  //compensate outputs   Loop for op = 1 to OP    Read fixture delayvalue of output      op_fxdl_val[n,k,op]    New_ui_fxdl_val[n,k,op] =ui_fxdl_val[n,k,op] +      Delta_t1[n,k]    Write new fixture delayvalue of output      New_ui_fxdl_val[n,k,op] to fd_merge   End loop op End loop k End loop N } Fixture_Delay_Calibration_for_Driver_Sharing( N= number of DUTs per shared bus K = number of shared buses per interfacefd[1:N] = fixture delay calibration files from      DUT[1:N,1:K]) {Fixture_Delay_Calibration(N,K) Post_Procesing_Procedure(N,K,fd[1:N]) }

Moreover, in the following an algorithm for a compensation of deviceloading effects will be described. The algorithm described in thefollowing takes into account the device loading and is described withpseudo-code. The following table shows a correspondence of symbols inthe text to variables used in the pseudo-code:

Symbol used in text Variable used in pseudo code DUTn on shared bus kDUT[n,k] Δt_(1n) Delta_t1[n,k] t_(L) Loading_effect Δt_(1N)[withdevices] Delta_t1_L[N,1] Δt_(1n)[with devices] Delta_t1[n,k]

The following listings describe some program routines, according to someembodiments of the present invention.

  Correction_Procedure_for_Loading_Effect ( N = number of DUTs pershared bus) { //it is sufficient to only measure the bus k = 1 and    DUT[n=N,k=1] //Analyze pin configuration Determine P = number ofpins per DUT Insert short circuit device into socket of DUT[N,1] bus[1]Insert N-1 regular devices into socket of DUT[1:N-1,1]     bus [1]Create fixture delay calibration file fd_L for DUT[N,1]     bus [1] Loopfor p = 1 to P  Measure fixture delay fxdl_val[p,1,N] of pin[p] ofbus[1]     and DUT[N,1] End loop p Write fixture delay valuesfxdl_val[1:P,1,N] to file fd_L }Post_Processing_Procedure_Including_Loading_Effect( N = number of DUTsper shared bus K = number of shared buses per interface fd[1:N] =fixture delay calibration files from DUT[1:N,1:K] fd_L = fixture delaycalibration file for DUT[N,1] bus[1]     with loading) { //Analyze pinconfiguration Determine SI = number of shared input per DUT Determine UI= number of unshared inputs per DUT Determine OP = number of outputs perDUT //extract device loading effect Open fixture delay calibration filefd_L of DUT[N,1] Open fixture delay calibration file fd[N] of DUT[N,1:K]Loop for si = 1 to SI  Read fixture delay value of shared input    si_fxdl_val_L[N,1,si] from fd_L  Read fixture delay value of sharedinput     si_fxdl_val[N,1,si] from fd[N]  Si_delta_t_L[N,1,si] =si_fxdl_val_L[N,1,si] −     si_fxdl_val[N,1,si]  End Loop siDelta_t1_L[N,1] = average over si (Si_delta_t_L[N,1,si]) Loading_effect= (Delta_t1_L[N, 1])/(N-1) Create new fixture delay calibration filefd_merge for the     whole interface //process DUT[1,1:K] data withoutcompensation Open fixture delay calibration file f[1] of DUT[1,1:k] Loopfor k = 1 to K  Loop for si = 1 to SI   Read fixture delay value ofshared input     si_fxdl_val[1,k,si] from fd[1]   Write fixture delayvalue of shared input     si_fxdl_val[1,k,si] to fd_merge  End loop si Loop for ui = 1 to UI   Read fixture delay value of shared input    ui_fxdl_val[1,k,ui] from fd[1]   Write fixture delay value of sharedinput     ui_fxdl_val[1,k,ui] to fd_merge  End loop ui  Loop for op = 1to OP   Read fixture delay value of output op_fxdl_val[1,k,op]     fromfd[1]   Write fixture delay value of output op_fxdl_val[1,k,op]     tofd_merge  End loop op End loop k //perform compensation for DUT[2:N,1:K]on unshared inputs     and output pins Loop for n = 2 to N  Open fixturedelay calibration file fd[n] of DUT[n,1:K] Loop for k = 1 to K   //calculate compensation value   Loop for si = 1 to SI    Read fixturedelay value of shared input     si_fxdl_val[n,k,si] from fd[n]   Si_delta_t[n,k,si] = si_fxdl_val[n,k,si] −     si_fxdl_val[1,k,si]  End loop si   Delta_t1[n,k]= average over si (Si_delta_t[n,k,si]) +    Loading_effect * (n-1)   // compensate unshared inputs   Loop for ui= 1 to UI    Read fixture delay value of unshared input    ui_fxdl_val[n,k,ui]    New_ui_fxdl_val[n,k,ui] = ui_fxdl_val[n,k,ui]−     Delta_t1[n,k]    Write new fixture delay data of unshared input    New_ui_fxdl_val[n,k,ui] to fd_merge   End loop ui   //compensateoutputs   Loop for op = 1 to OP    Read fixture delay value of output    op_fxdl_val[n,k,op]    New_ui_fxdl_val[n,k,op] =ui_fxdl_val[n,k,op] +     Delta_t1[n,k]    Write new fixture delay valueof output     New_ui_fxdl_val[n,k,op] to fd_merge   End loop op  Endloop k End loop N }Fixture_Delay_Calibration_for_Driver_Sharing_Including_Load ing_Effect(N = number of DUTs per shared bus K = number of shared buses perinterface) { Fixture_Delay_Calibration(N,K) Correction_Procedure_for_Loading_Effect(N) Post_Procesing_Procedure(N,K,fd[1:N],fd_L) }

To summarize the above description, it can be stated that thedescription provides an overview of a solution proposal for a fixturedelay calibration when using driving sharing interfaces. The problemunderlying the present invention can be summarized as follows: Due to asharing of single tester driver channels for multiple device inputs,multiple different propagation delays in the interface may need to becompensated for each shared driver. The compensation should take intoaccount a signal path from a pogo interface to individual duts connectedto a shared bus. Since fixture delay calibration delay can onlycompensate a single path to one dut board, the above described newsolution has been developed to also compensate a signal path to otherduts connected to one shared bus. Embodiments of the above describedinvention allow for an efficient calibration and also bring along thepossibility to operate test setups with driver sharing at very highspeed without compromising reliability of the test results.

While this invention has been described in terms of several embodiments,there are alterations, permutations, and equivalents which fall withinthe scope of this invention. It should also be noted that there are manyalternative ways of implementing the methods and compositions of thepresent invention. It is therefore intended that the following appendedclaims be interpreted as including all such alterations, permutationsand equivalents as fall within the true spirit and scope of the presentinvention.

1. A chip tester for testing at least two devices under test connectedto the chip tester, wherein at least a first terminal of the a firstdevice under test and a first terminal of a second device under test areconnected to a first channel of the chip tester via a shared line,wherein a second terminal of the first device under test is connected toa second channel of the chip tester via an unshared line, and wherein asecond terminal of the second device under test is connected to a thirdchannel of the chip tester via an unshared line, the chip testercomprising: a timing calculator for generating a timing information forthe channels of the chip tester, wherein the timing calculator isadapted to acquire a propagation delay difference information describinga difference between, on the one hand, a propagation delay from a firstchannel port of the chip tester to the first terminal of the firstdevice under test and, on the other hand, a propagation delay from thefirst channel port of the chip tester to the first terminal of thesecond device under test, and wherein the timing calculator is adaptedto provide timing information to adjust a timing shift between timingsof the second channel and the third channel on the basis of thepropagation time difference information; and a channel moduleconfigurator adapted to configure the second channel and/or the thirdchannel of the chip tester on the basis of the timing information. 2.The chip tester of claim 1, wherein the timing calculator is adapted toprovide a timing information both for the second channel.
 3. The chiptester of claim 1, wherein the second channel and the third channel areadapted to provide, shifted in time with respect to each other,identical data patterns to the second terminal of the first device undertest and to the second terminal of the second device under test.
 4. Thechip tester of claim 1, wherein: the second channel of the chip testeris configured to be an output channel, the third channel of the chiptester is configured to be an output channel, and the timing calculatorand the channel module configurator are adapted to adjust output timingsof the second channel and the third channel such that a relative timingof signals reaching the first terminal and the second terminal of thefirst device under test is at least approximately identical to arelative timing of signals reaching the first terminal and the secondterminal of the second device under test.
 5. The chip tester of claim 4,wherein the timing calculator and the channel module configurator areadapted to effect a delay of an output timing of the third channel withrespect to an output timing of the second channel, if the propagationdelay from the first channel port of the chip tester to the firstterminal of the first device under test is larger than the propagationdelay from the first channel port of the chip tester to the firstterminal of the second device under test.
 6. The chip tester of claim 1,wherein: the second channel of the chip tester is configured to be aninput channel, the third channel of the chip tester is configured to bean input channel, and the timing calculator and the channel moduleconfigurator are adapted to adjust input timings of the second channeland the third channel such that a relative timing between a signalreaching the first terminal of the first device under test and aneffective dut signal value sample time of the second channel is at leastapproximately identical to a relative timing between a signal reachingthe first terminal of the second device under test and an effective dutsignal value sample time of the third channel, wherein the effective dutsignal value sample time defines, when a signal sampled in a channel hasbeen present at a dut terminal.
 7. The chip tester of claim 6, whereinthe timing calculator and the channel module configurator are adapted toadjust input clocks of the second channel and the third channel, inorder to set the effective dut signal value sample times, wherein theinput clock of the second channel defines an instance in time when thesignal provided by the second terminal of the first device under test issampled or compared with a reference value, and wherein the input clockof the third channel defines an instance in time when the signalprovided by the second terminal of the second device under test issampled or compared with a reference value.
 8. The chip tester of claim6, wherein the second channel of the chip tester and the third channelof the chip tester are configured to compare, shifted in time withrespect to each other, a data pattern provided by the second terminal ofthe first device under test and a data pattern provided by the secondterminal of the second device under test with identical reference datapatterns.
 9. The chip tester of claim 6, wherein the timing calculatorand the channel configurator are adapted to delay a timing of the thirdchannel with respect to a timing of the second channel, if thepropagation delay from the first channel port of the chip tester to thefirst terminal of the first device under test is larger than thepropagation delay from the first channel port of the chip tester to thefirst terminal of the second device under test.
 10. The chip tester ofclaim 1, wherein the chip tester is adapted to adjust timings ofdifferent channels individually.
 11. The chip tester of claim 1, whereinthe chip tester is adapted to acquire the propagation delay differenceinformation by performing at least one time-domain-reflectionmeasurement.
 12. The chip tester of claim 1, wherein the chip tester isadapted to acquire the propagation delay difference information byreading the propagation delay difference information from a file. 13.(canceled)
 14. (canceled)
 15. (canceled)
 16. The chip tester of claim 1,wherein the timing calculator is adapted to acquire an averagedpropagation delay difference information by averaging propagation delaydifference information for a plurality of shared channels, each of theshared channels being connectable both to a terminal of the first deviceunder test and to a terminal of the second device under test.
 17. Thechip tester of claim 1, wherein the chip tester is adapted to adjust atiming of at least one channel coupled to a given device under test independence on whether a device under test is loaded in another deviceunder test socket or not.
 18. The chip tester of claim 17, wherein thechip tester is adapted to acquire a loading state dependent propagationdelay information describing a propagation delay between a channel portand terminal connections of a given device under test in differentloading states of a line connecting the channel port and the givendevice under test, and to apply the loading state dependent propagationdelay information to adjust the timing of the at least one channelcoupled to the given device under test.
 19. The chip tester of claim 18,wherein the chip tester is adapted to acquire an unloaded-statepropagation delay information describing a propagation delay between thechannel port and terminal connections for at least a first device undertest, a second device under test and a third device under testconnectable to the channel port via a shared line; to acquire aloaded-state propagation delay between the channel port and a terminalconnection under consideration with at least one device under test loadbeing arranged electrically between the channel port and the terminalconnection under consideration; and to provide an estimate for aloaded-state propagation delay between the channel port and at least onefurther terminal connection by means of a calculation based on theassumption that each device under test load electrically between thechannel port and the device under test connection, for which thecalculation is performed, contributes an identical propagation delay.20. The chip tester of claim 17, wherein the chip tester is adapted toadjust a timing of at least one channel during the execution of a testrun in response to a signal indicating that a device under test socketwill no longer be loaded by a device under test socket loadingmechanism.
 21. (canceled)
 22. A test fixture set, comprising: a deviceunder test board for providing an electrical connection between a chiptester and at least two devices under test, the device under test boardcomprising a first device under test contact element for providing adetachable electrical contact between the device under test board and afirst device under test, a second device under test contact element forproviding a detachable electrical contact between the device under testboard and a second device under test, a third device under test contactelement for providing a detachable electrical contact between the deviceunder test board and the first device under test, a fourth device undertest contact element for providing a detachable electrical contactbetween the device under test board and the second device under test, afirst chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, asecond chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, and athird chip tester contact element for providing a detachable electricalcontact between the device under test board and the chip tester, whereinthe first device under test contact element and the second device undertest contact element are both electrically connected to the first chiptester contact element via a shared line; wherein the third device undertest contact element is electrically connected to the second chip testercontact element; wherein the fourth device under test contact element iselectrically connected to the third chip tester contact element; and adata exchange medium or data stream for usage with the chip tester, thedata exchange medium or data stream comprising an effective propagationdelay information describing an effective propagation delay between thethird device under test contact element and the second chip testercontact element and an effective propagation delay between the fourthdevice under test contact element and the third chip tester contactelement, wherein the effective propagation delays are based on actualpropagation delays and wherein at least one of the effective propagationdelays is changed with respect to a corresponding actual propagationdelay, such that the deviation of the effective propagation delay fromthe actual propagation delay reflects a difference between, on the onehand, a propagation delay between the first chip tester contact elementand the first device under test contact element and, on the other hand,a propagation delay between the first chip tester contact element andthe second device under test contact element.
 23. The test fixture setof claim 22, further comprising: a fifth device under test contactelement for providing an electrical contact between the device undertest board and the first device under test, a sixth device under testcontact element for providing an electrical contact between the deviceunder test board and the second device under test and a fourth chiptester contact element for providing a detachable electric contactbetween the device under test board and the chip tester; wherein thefifth device under test contact element and the sixth device under testcontact element are both electrically coupled to a fourth chip testercontact element via a second shared line, wherein a portion of the firstshared line between the first device under test contact element and thesecond device under test contact element is length-matched to a portionof the second shared line between the fifth device under test contactelement and the sixth device under test contact element.
 24. Anapparatus for post-processing a plurality of propagation delay values ofa device under test board for a chip tester, wherein the device undertest board is adapted to provide an electrical connection between a chiptester and at least two devices under test, and wherein the device undertest board comprises a first device under test contact element forproviding a detachable electrical contact between the device under testboard and a first device under test, a second device under test contactelement for providing a detachable electrical contact between the deviceunder test board and a second device under test, a third device undertest contact element for providing a detachable electrical contactbetween the device under test board and the first device under test, afourth device under test contact element for providing a detachableelectrical contact between the device under test board and the seconddevice under test, a first chip tester contact element for providing adetachable contact between the device under test board and the chiptester, a second chip tester contact element for providing a detachablecontact between the device under test board and the chip tester, a thirdchip tester contact element for providing a detachable electricalcontact between the device under test board and a chip tester, whereinthe first device under test contact element and the second device undertest contact element are both electrically connected to the first chiptester contact element via a shared line, the apparatus comprising: apropagation delay determinator for acquiring an original propagationdelay value describing a propagation delay between the fourth deviceunder test contact element and the third chip tester contact element; apropagation delay difference value determinator for acquiring apropagation delay difference value describing a difference between, onthe one hand, a propagation delay between the first chip tester contactelement and the first device under test contact element and, on theother hand, a propagation delay between the first chip tester contactelement and the second device under test contact element; and apropagation delay modifier for modifying the original propagation delayvalue on the basis of the propagation delay difference value. 25.(canceled)
 26. The apparatus of claim 24, wherein the apparatus isadapted to leave original propagation delay values describing apropagation delay between the first chip tester contact element of thedevice under test board and the corresponding first device under testcontact element for a first device under test, which is locatedelectrically closest to the first chip tester contact element,unchanged.
 27. The apparatus of claim 24, wherein the apparatus forpost-processing is adapted to provide an effective propagation delayvalue describing an effective propagation delay between the fourthdevice under test contact element and the third chip tester contactelement by subtracting the difference between, on the one hand, apropagation delay between the first chip tester contact element and thefirst device under test contact element and, on the other hand, thepropagation delay between the first chip tester contact element and thesecond device under test contact element, from the original propagationdelay value describing, at least approximately, the actual propagationdelay between the fourth contact element and the third chip testercontact element.
 28. The apparatus of claim 24, wherein the apparatusfor post-processing is adapted to provide an effective propagation delayvalue describing an effective propagation delay between the fourthdevice under test contact element and the third chip tester contactelement by adding the difference between, on the one hand, a propagationdelay between the first chip tester contact element and the first deviceunder test contact element and, on the other hand, the propagation delaybetween the first chip tester contact element and the second deviceunder test contact element, to the original propagation delay valuedescribing, at least approximately, the actual propagation delay betweenthe fourth contact element and the third chip tester contact element.29. The apparatus of claim 27, wherein the apparatus for post-processingis adapted to receive a terminal direction information describingwhether the second terminal of the second device under test is used inan input terminal or as an output terminal, and to decide, whether toacquire the effective propagation delay by adding or by subtracting, independence on the terminal direction information.
 30. The apparatus ofclaim 24, wherein the apparatus for post-processing is adapted to mergea plurality of files describing propagation delay values for a pluralityof device under test positions into a single file.
 31. The apparatus ofclaim 29, wherein the apparatus for post-processing is adapted to avoidproviding a negative effective propagation delay value by applying anadditional offset value to the effective propagation delay values.
 32. Amethod for post-processing a plurality of propagation delay values for adevice under test board for a chip tester, wherein the device under testboard is adapted to provide an electrical connection between the chiptester and at least two devices under test, and wherein the device undertest board comprises a first device under test contact element forproviding a detachable electrical contact between the device under testboard and a first device under test, a second device under test contactelement for providing a detachable electrical contact between the deviceunder test board and a second device under test, a third device undertest contact element for providing a detachable electrical contactbetween the device under test board and the first device under test, afourth device under test contact element for providing a detachableelectrical contact between the device under test board and the seconddevice under test, a first chip tester contact element for providing adetachable electrical contact between the device under test board andthe chip tester, a second chip tester contact element for providing adetachable electrical contact between the device under test board andthe chip tester, and a third chip tester contact element for providing adetachable electrical contact between the device under test board and achip tester, wherein the first device under test contact element and thesecond device under test contact element are both electrically connectedto the first chip tester contact element via a shared line, the methodcomprising: acquiring an original propagation delay value describing apropagation delay between the fourth device under test contact elementand the third chip tester contact element; acquiring a propagation delaydifference value describing a difference between, on the one hand, apropagation delay between the first chip tester contact element and thefirst device under test contact element, and, on the other hand, apropagation delay between the first chip tester contact element and thesecond chip tester contact element; and modifying the originalpropagation delay value using the propagation delay difference value.33. (canceled)
 34. (canceled)
 35. (canceled)
 36. (canceled)
 37. A methodfor providing timing information for adjusting a timing of a chip testeroperating in a configuration in which at least a first terminal of afirst device under test and a first terminal of a second device undertest are connected to a first channel of the chip tester via a sharedline and in which a second terminal of the first device under test isconnected to a second channel of the chip tester via an unshared lineand in which a second terminal of the second device under test isconnected to a third channel of the chip tester via an unshared line,the method comprising: acquiring a propagation delay differenceinformation describing a propagation time difference between, on the onehand, the propagation delay from a first channel port of the chip testerto the first terminal of the first device under test, and, on the otherhand, a propagation delay from the first channel port of the chip testerto the first terminal of the second device under test; and providing thetiming information to adjust a timing shift between timings of thesecond channel and the third channel on the basis of the propagationtime difference information.